1. Field of the Invention
The present invention relates to techniques for fabricating a semiconductor device that includes both an enhancement-mode FET (enhancement-mode Field Effect Transistor) and a depletion-mode FET (depletion-mode Field Effect Transistor).
2. Description of the Related Art
Field effect transistors (FETs) such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) have been widely used for semiconductor integrated circuits such as drive circuits of liquid crystal displays, and decode circuits of RAMS (Random Access Memories) or ROMs (Read Only Memories). One type of such semiconductor integrated circuits is the integrated circuit in which two types of FETs, enhancement-mode FETs and depletion-mode FETs, are integrated on a semiconductor substrate. For example, Japanese Patent Application Publication No. H11-174405 discloses a drive circuit of a liquid crystal display in which enhancement-mode and depletion-mode FETs are integrated.
The problem with the integration of different types of FETs (i.e., enhancement-mode FETs and depletion-mode FETs) on the semiconductor substrate is that the fabrication process including the integration of different types of FETs becomes more complicated compared with that including integration of the same type of FETs, thus resulting in relatively high cost. An example of such a problem will be described with reference to FIGS. 1-3.
FIG. 1 schematically illustrates a geometrical configuration of gate electrodes 101, 102, 103 and 104 formed over active regions 111, 112 and 113. FIG. 2 schematically illustrates a cross-sectional view of a semiconductor structure as taken along line II-II of FIG. 1. The strip-shaped active regions 111-113 as illustrated in FIG. 1 extend in the X-axis direction. These active regions 111-113 are electrically separated from one another by an isolation structure such as a STI (Shallow Trench Isolation) structure. For example, as illustrated in FIG. 2, the active region 111 can be surrounded by isolation structures 120a and 120b. The gate electrodes 101-104 are formed over the active regions 111-113, and arranged in the Y-axis direction. An insulating film 123 is interposed between the gate electrodes 101-104 and the active regions 111-113. In the top view of FIG. 1, the insulating film 123 is not shown for the sake of convenience.
FETs will be formed in or in the vicinity of the overlapping regions in which the gate electrodes 101-104 extend over the active regions 111-113. These overlapping regions include the regions 102Da, 102Db and 103Da in or in the vicinity of which depletion-mode FETs will be formed. In these regions 102Da, 102Db and 103Da, doped regions for depletion-mode FETs will be formed directly under the gate electrodes 102, 103 in order to control the threshold voltages of the depletion-mode FETs. FIG. 3 schematically illustrates a cross-sectional view of a semiconductor structure produced by a fabrication step of forming a doped region in the region 102Da in order to control the threshold voltage of a depletion-mode FET. As illustrated in FIG. 3, a resist pattern 130 is formed by photolithography. The resist pattern 130 covers the underlying gate electrodes 101, 103 and 104 for enhancement-mode FETs. This resist pattern 130 also has an opening 130h in which the gate electrode 102 for the depletion-mode FET is not covered by the resist pattern 130. Dopant impurities 131 are ion-implanted into the semiconductor substrate 100 using the resist pattern 130 as a mask, thereby to form doped regions 132 for controlling the threshold voltage of the depletion-mode FET. P-type dopants such as Boron (B) for a p-channel FET or n-type dopants such as Arsenic (As) for an n-channel FET can be ion-implanted as the dopant impurities. After the ion-implantation, the resist pattern 130 is removed.
Next, various processes will be performed to fabricate the depletion-mode and enhancement-mode FETs. For example, sidewall spacers (not shown) are formed on the opposite sides of each of the gate electrodes 101, 102, 103 and 104. Dopant impurities are then ion-implanted using as a mask the sidewall spacers, the isolation structures 120a, 120b and the gate electrodes 101, 102, 103 and 104, thereby to form doped regions (not shown) for LDD (Lightly Doped Drain) regions on the opposite sides of each of the gate electrodes 101, 102, 103 and 104.
The problem with the above fabrication process is that the photolithography as described above is required to form the doped region 132 for controlling the threshold voltage of the depletion-mode FET. This results in high cost compared with other fabrication processes for forming only enhancement-mode FETs on a semiconductor substrate.
In view of the foregoing, it is an object of the present invention to provide a method of fabricating a semiconductor device capable of reducing manufacturing cost in forming enhancement-mode and depletion-mode FETs which are integrated on a semiconductor substrate.